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Dr. G. Ramana Murthy

Professor

Alliance College of Engineering and Design

Dr. G. Ramana Murthy teaches various subjects at undergraduate and postgraduate levels related to the field of Electronics and Communication Engineering. His area of expertise is in VLSI and Embedded Systems. Dr. Murthy holds a Doctorate of Philosophy from Multimedia University, Malaysia on “Design of low power multiplexer based adders for Digital IIR Filter”.

Dr. Murthy has collaborated with various companies including Infenion Technologies, Intel, and MIMOS in Malaysia. He has over two decades of overseas academic and administrative experience with institutions such as University of Northumbria Newcastle from UK, Multimedia University, Malaysia. He is involved as Project Leader for various projects funded by the University, Ministry of Science, Technology, and Innovation (Ministry of Higher Education and Telekom Malaysia). He is a reviewer and an editorial board member for internationally recognized journals. He served as reviewer for external research granted projects under MOSTI and MOHE.

His research interests include VLSI, embedded systems, device modeling, Memory optimization, low power design, FPGA, and evolutionary algorithms.

WoS/ISI

  • Gajula Ramana Murthy, Sharad Tiwari (2021) “Analysis of short channel effects in symmetric junction less double gate doped MOSFET using Atlas 2-D simulator” Analog Integrated Circuits and Signal Processing (under review).
  • Gajula Ramana Murthy, Sharad Tiwari and Sarada Marasu “Impact of Dielectric materials on FinFET Characteristics at 45nm using Silvaco Atlas 2-D Simulations” Science International (Lahore) Vol .33, No. 1, pp. 61-64, Feb 2021. (WoS, IF 1.852)
  • Z. H. Jesmeen, G. Ramana Murthy, J. Hossen, Jaya Ganesan, A. Abd Aziz, K. Tawsif “Detecting abnormal electricity usage using unsupervised learning model in unlabeled data” International Journal of Advanced and Applied Sciences, Vol. 8, No. 9, pp. 102-111, Sep 2021.
  • Shahmini Subramaniam, Ajay Kumar Singh and Gajula Ramana Murthy “Design of power efficient stable 1-bit full adder circuit” IEICE Electronics Express, Vol.15, No.14, pp.1-6, Jul 2018. (WoS Q4, IF 0.586)
  • Ajay Kumar Singh, B. Naresh Kumar, G. Ramana Murthy, C.M.R Prabu “A Comprehensive Analytical Study of Electrical Properties of Carbon nano-tube Field effect transistor (CNTFET) for future nano-technology” International Journal of Numerical Modelling: Electronic Networks, Devices and Fields, Vol. 31, No. 1, Jan/Feb 2018: e2261. (WoS Q4, IF 0.816)
  • Ramana Murthy, Ajay Kumar Singh, P. Velraj Kumar, Tan Wee Xin Wilson “Design of a Low Power and High-Speed Comparator using Mux based Full Adder Cell for Mobile Communications” American Journal of Applied Sciences, Vol. 14, No. 1, pp. 116-123, Jan 2017. (WoS Q3, IF 0.896)
  • Ramana Murthy, C. Senthilpari, P. Velrajkumar, and Lim Tien Sze “Monte-Carlo analysis of a new 6-T Full-Adder Cell for Power and Propagation Delay Optimizations in 180nm Process” Engineering Computations, Vol. 31, No. 2, pp. 149-159, Apr 2014. (WoS Q2, IF 1.206)
  • Ramana Murthy, C. Senthilpari, P. Velrajkumar and Lim Tien Sze “A new 6-T multiplexer based Full-Adder for low Power and Leakage current optimization” IEICE, Electronics Express. Vol. 9, No. 17, pp. 1434-1441, Sep 2012. (WoS Q4, IF 0.268)
  • Pitchandi Velrajkumar, C. Senthilpari, G. Ramana Murthy, E K Wong, “Bit-Parallel iterative circuit for robotic application”, IEICE Electronic Express, Vol. 9, No. 6, pp. 443-449, Mar 2012. (WoS Q4, IF 0.461)
  • Senthil Arumugam Muthukumaraswamy, Aarthi Chandramohan, Ramana Murthy Gajula, “On the Optimal Control of Steel Annealing Processes via various versions of Genetic and Particle Swarm Optimization Algorithms” Optimization and Engineering. DOI 10.1007/s11081-011-9143-5, Apr 2011. (WoS Q2, IF 0.852)
  • Senthil Arumugam, G. Ramana Murthy, and C.K.Loo "On the Optimal Control of the Steel Annealing Processes as a Two-Stage Hybrid Systems via Particle Swarm Optimization Algorithms" International Journal of Bio-Inspired Computation (IJBIC), Vol. 1, No. 3, pp. 198-209. DOI: 10.1504/IJBIC.2009.023815. (WoS Q1, IF 3.395)
  • Ramana Murthy, M.Senthil Arumugam and C.K.Loo “Hybrid Particle Swarm optimization algorithms with fine tuning operators” International Journal of Bio-Inspired Computation (IJBIC), Vol.1, Nos.1/2, pp.14-31. DOI: 10.1504/IJBIC.2009.02771. (WoS Q1, IF 3.395)

Scopus

  • Velrajkumar, C. Senthilpari, G. Ramana Murthy, E.K. Wong (2021) “A Power and Speed efficient PTL-based bit parallel Iterative CORDIC circuit for am application in Mobile Robot exploration” Pertanika Journal of Science and Technology. (in press).
  • Hima Bindu Katikala, G Ramana Murthy, P RajaRajeswari, P Sai Charan, Sd Kashif Irfan, “Estimation of Write Noise Margin for 6t SRAM Cell in CMOS 45nm technology” Journal of University of Shanghai for Science and Technology, Vol 23, Issue 5, pp. 211-215, May 2021.
  • Nazir S, Azlan Bin Abd Aziz, J. Hossen, Jaya Ganesan, Nor Azlina Aziz, Ramana Murthy G “An Evaluation of Deep Neural Network Models on Short-term Energy Consumption Forecasting for Smart Home Management System” International Journal of Mechanical & Mechatronics Engineering IJMME/IJENS, Vol 21, No 1, pp. 42-47, Feb 2021.
  • Velrajkumar, C.Senthilpari, P.Ramesh, G.Ramana Murthy, D.Kodandapani “Development of Smart Number Writing Robotic Arm using Stochastic Gradient Decent Algorithm” International Journal of Innovation Technology and Exploring Engineering, Vol. 8, No. 10, pp. 542-547, Aug 2019. (Scopus New Index)
  • M.H. Arif, J. Hossen, G. Ramana Murthy, Jesmeen M. Z. H., J. Emerson Raja “An efficient microcontroller based sun tracker control for solar cell systems” International Journal of Electrical and Computer Engineering, Vol. 9, No. 4, pp. 2742-2750, Aug 2019. (Scopus Q2, IF 0.368)
  • Leo Bermudez Pestañas, G. Ramana Murthy, A. Kumar Singh “Appliation of SAR 32-bit SAR A/D conversion for vibration, impact and shock data logging” Journal of Engineering and Applied Sciences, Vol. 30, No. 20, pp. 8382-8390, Nov. 2018. (Scopus Q3, IF 0.141)
  • M. H. Arif, J. Hossen, G. Ramana Murthy, Tawsif K., Jesmeen M. Z. H. and Ferdous Hossain “A survey on neuro-fuzzy controller based solar panel tracking system” Far East Journal of Electronics and Communications, Vol. 8, No. 7, pp. 981-1003, Oct 2018. (Scopus Q4, IF 0.114)
  • Leo Bermudez Pestañas, G. Ramana Murthy and Ajay Kumar Singh “Implementation of 32-bit Sigma-Delta (Σ?) A/D Conversion for Thermal Diode Acquisition Unit (TDAU)” ARPN Journal of Engineering and Applied Sciences. Vol. 12, No. 24, pp. 7096-7103, Dec 2017. (Scopus Q3, IF 0.189)
  • Ramana Murthy, Ajay Kumar Singh, Md. Jakir Hossen, P.Velraj Kumar “Performance Analysis of Electrical Characteristics for Short Channel Effects (SCE) in Carbon Nano Tube Field Effect Transistor (CNTFET) Devices” Journal of Engineering and Applied Sciences, Vol. 12, No. 20, pp. 5116-5120, 2017. (Scopus Q3, IF 0.163)
  • Velrajkumar, G. Ramana Murthy, Joseph Emerson Raja, Md. Jakir Hossen, Lo Kok Jong “Controlling and Tracking of Mobile Robot in Real Time using Android Platform” Journal of Engineering and Applied Sciences, Vol. 12, No. 4, pp. 929-932, 2017. (Scopus Q3, IF 0.163)
  • Ramana Murthy, Ajay Kumar Singh, P.Velraj Kumar “A Symmetric Double-Gate MOSFET in Presence of Quantum Confinement” Australian Journal of Basic and Applied Sciences, Vol. 9, No. 36, pp. 193-197, Dec 2015. (Scopus Q4, IF 0.126)
  • Velrajkumar, C. Senthilpari, G. Ramana Murthy, E.K. Wong “Low Energy, Improved Speed and High Throughput CORDIC Cell to Improve Performance of Robots’ Processor” Asian Journal of Scientific Research, Vol. 8, No. 3, pp. 381-391, Jul 2015. (Scopus Q1, IF 0.381)
  • Velrajkumar, C. Senthilpari, G. Ramana Murthy, E.K. Wong” Design of low power COrdic based robotic processor to improve the performance of Armdroid robot” Australian Journal of Basic and Applied Sciences, Vol. 8, No. 6, pp. 251-256, Apr 2014. (Scopus Q4, IF 0.133)
  • Velrajkumar, C.Senthilpari, G. Ramana Murthy, E.K. Wong.” Design of low EPI and high throughput Cordic cell to improve the performance of mobile robot”, Journal of Engineering Science and Technology, Vol. 9, No. 2, pp. 167-175, Apr 2014. (Scopus Q3, IF 0.175)
  • Senthilpari, Rosalind Deena Kumari, K. Diwakar, P. Velrajkumar, G. Ramana Murthy. “Low power and 5.8 GHz operating frequency of digital frequency divider using proposed sequential circuit” Australian Journal of Basic and Applied Sciences, Vol. 8, No.1, pp. 273-281, Feb 2014. (Scopus Q4, IF 0.133)
  • Ramana Murthy, C. Senthilpari, P. Velrajkumar and Lim Tien Sze “A Novel Design of Multiplexer based Full-adder Cell for Power and Propagation Delay Optimizations” Journal of Engineering Science and Technology, Vol. 8, No. 6, pp.764-777, Dec 2013. (Scopus Q3, IF 0.175)
  • Ramana Murthy, C. Senthilpari, P. Velrajkumar and Lim Tien Sze “Design of Low Power and High-Speed Digital IIR Filter in 45nm with Optimized CSA for Digital Signal Processing Applications” World Academy of Science Engineering and Technology, Vol. 7, No. 4, pp. 164-171, Apr 2013. (Scopus Q4, IF 0.124)
  • Ramana Murthy, C. Senthilpari, P. Velrajkumar and Lim Tien Sze “Monte-Carlo analysis of a new 6-T Full-Adder Cell for Power and Propagation Delay Optimizations in 180nm Process”, Applied Mechanics and Materials, Vols. 284-287, pp. 2580-2589, Jan 2013. (Scopus Q4, IF 0.123)
  • Pitchandi Velrajkumar, C. Senthilpari, G. Ramana Murthy, E K Wong,” Proposed adder and modified LUT bit parallel unrolled CORDIC circuit for an application in mobile robots” Asian Journal of Scientific Research, 6, No. 4, pp. 666-678, Jan 2013. (Scopus Q1, IF 0.305)
  • Senthilpari, P. Velrajkumar, G. Ramana Murthy and J. Emerson raja, Low-Power, High-Throughput, Unsigned Multiplier Using A Modified CPL Adder Cell for Signal Processing Circuit, Australian Journal of Basic and Applied Sciences, Vol. 6, No. 12, pp. 123-130, Dec 2012. (Scopus Q3, IF 0.174)
  • Ramana Murthy, C. Senthilpari, P.Velrajkumar, Lim Tien Sze, “Interconnect Analysis of a Novel Multiplexer Based Full-Adder Cell for Power and Propagation Delay Optimizations”, World Academy of Science Engineering and Technology, Vol. 6, pp. 299-303, Mar 2012. (Scopus Q4, IF 0.12)
  • Senthilpari, G. Ramana Murthy, P.Velrajkumar, “An Efficient EPI and Energy Consumption of 32 bit ALU Using Shannon Theorem Based Adder Approach”, WSEAS Transactions on Circuits and Systems, Vol. 10, No. 7, pp. 231-238, Sep 2011. (Scopus Q3, IF 0.225)

Awards/Recognition

  • Best researcher award Faculty of Engineering and Technology, Multimedia University, Malaysia. (March and August 2019)
  • Charted Engineer recognition from Engineering Council, UK 2013.
  • Senior member IEEE
  • Member IET
  • Life member IAENG, Japan.
  • Board of Engineers (Electronics) Malaysia recognition, 2019.
  • Certified Train the Trainer recognition from HRDF, Ministry of Human Resource Malaysia, 2017

Patent

  • IoT based user location discovery identification for future smart home by using solenoid electromagnetic cabinet sensor.
    Australian Government, IP Australia No: 2021100915

IPs

  • Time series forecasting for smart home energy system with data anomaly detection. (Telekom Malaysia)
  • A prediction framework of energy consumption based on IoT time series missing value data sets. (Telekom Malaysia)

Consultancy

  • MRL Engineering Sdn Bhd, Malacca, Malaysia.
  • Infineon Technologies, Malacca, Malaysia.
  • Altran, Penang, Malaysia.
  • Maruwa Sdn Bhd, Malaysia

  • S. R. Manchala and G. Ramana Murthy, "Low-Power and Low-Leakage Design Techniques in CMOS Technology," 5th International Conference on Trends in Electronics and Informatics (ICOEI), 2021, pp. 273-278.
  • Hima Bindu Katikala, G Ramana Murthy “A Design of Current Starved Inverter-Based Non-overlap Clock Generator for CMOS Image Sensor” Intelligent Systems: Proceedings of SCIS 2021, pp. 115-124.
  • Nazir, Azlan Ab Aziz, J. Hosen, Nor Azlina Aziz, G. Ramana Murthy “Forecast Energy Consumption Time-Series Dataset using Multistep LSTM Models” Journal of Physics: Conference Series, 1933 (2021) 012054.
  • Spandana B, Ramana Murthy G “Design of DLMS Adaptive Filter with CSA and Baugh Wooley Multiplier for High Speed and Low Power” 4th National Conference on VLSI, Signal Processing and Communications, NCVSComs-2020, VFSTR, Vadlamudi, India, 18-19th Dec 2020.
  • Venkat Subbarao M, Ramana Murthy G “Low-Power and Low-Leakage Design Techniques in CMOS Technology”  4th National Conference on VLSI, Signal Processing and Communications, NCVSComs-2020, VFSTR, Vadlamudi, India, 18-19th Dec 2020.
  • Hima Bindu K, Ramana Murthy G “Design and implementation of High Performance Low pass Filter for Biomedical Implantable applications” 4th National Conference on VLSI, Signal Processing and Communications, NCVSComs-2020, VFSTR, Vadlamudi, India, 18-19th Dec 2020.
  • Jesmeen M. Z. H, Ramana Murthy G, Hossen J, Jaya Ganesan, Abd Aziz A, Tawsif, K “Detecting Abnormal Electricity Usage using Gaussian Mixture Model in Unlabelled Data” 4th National Conference on VLSI, Signal Processing and Communications, NCVSComs-2020, VFSTR, Vadlamudi, India, 18-19th Dec 2020.
  • Jaya Ganesan, G. Ramana Murthy, Balakanes Loganathan, Syed Nazir Hussein “Stakeholder Perceptions on Internet of Things (IoT) and Smart Digital Workplace” 11th Global Conference on Business and Social Science Series, Bangkok, Thailand, 11-12th Dec 2020.
  • M.H.Arif, J.Hossen, G.Ramana Murthy,Tajrian Mollick, Thangavel Bhuvaneswari, C. Venkataseshaiah “Performance Comparisons of Fuzzy Logic and Neuro-Fuzzy Controller Design in Solar Panel Tracking Systems” IEEE Conference on Systems, Process and Control, Melaka, Malaysia, 14-15th Dec 2018.
  • M.H. Arif, J. Hossen, G. Ramana Murthy, Md. Armanur Rahaman, “A Novel PID Controller based Solar Panel Tracking System” SEMA 2018, Symposium on Electrical, Mechatronics and Applied Science, UTeM, Melaka, Malaysia, 8th Nov 2018.
  • Shahmini Subramaniam, Ajay Kumar Singh and G. Ramana Murthy “Proposed reliable 16-bit pass transistor logic based full adder circuit design” SEMA 2018, Symposium on Electrical, Mechatronics and Applied Science, UTeM, Melaka, Malaysia, 8th Nov 2018.
  • B. Pestañas, G. Ramana Murthy, A. Kumar Singh “ARM Based 32bit Precision Angular Degree Movement Sensing for Any Rotary Shaft Mechanism” 9th International Conference on Humanoid, Nanotechnology, Information Technology, Communication and Control, Environment, and Management (HNICEM), Manila, Philippines, Dec 1-3, 2017.
  • Shahmini Subramaniam, Tan Wee Xin Wilson, Ajay Kumar Singh and G. Ramana Murthy “A Proposed Reliable and Power Efficient 14T Full Adder Circuit Design” TENCON: IEEE Region 10 Conference, Penang, Malaysia, 5-8 Nov 2017.
  • Ramana Murthy, C. Senthilpari, P.Velrajkumar, and Lim Tien Sze " RLC Modeling of Multiplexer Based Full-Adder for Power and Propagation delay Optimizations” IEEE International Conference on Circuits and Systems, Kuala Lumpur, Malaysia, 18-19 Sep 2013.
  • Ramana Murthy, C. Senthilpari, P.Velrajkumar, and Lim Tien Sze “Monte-Carlo analysis of a new 6-T Full-Adder Cell for Power and Propagation Delay Optimizations in 180nm Process” The 2nd International Conference on Engineering and Technology Innovation Kaohsiung, Taiwan, 02-06 Nov 2012.
  • Senthilpari, P.Velrajkumar and G. Ramana Murthy “A high operating frequency 65nm digital frequency divider for multimedia applications” MAL technical & Innovation Symposium at Infineon, Melaka, 2012.
  • Ramana Murthy, C. Senthilpari, P.Velrajkumar, Lim Tien Sze, “Leakage Current Optimization For Novel MUX-Based Full-Adder Cell In CMOS 130nm Technology” TENCON 2011, Bali, Indonesia, 21-24 Nov 2011 Page(s):734-738.
  • Senthil Arumugam, M. Ramana Murthy, G.  Rao, M.V.C.  Loo, K. “On the optimal control of the steel annealing processes as a two-stage hybrid system via different versions of PSO algorithms” Intelligent and Advanced Systems, 2007.ICIAS 2007. International Conference on 25-28 Nov. 2007 Page(s):522-527.
  • Senthil Arumugam, M. Ramana Murthy, G. Rao, M.V.C. Loo, C K. “A novel effective particle swarm optimization like algorithm via extrapolation technique” Intelligent and Advanced Systems, 2007. ICIAS 2007. International Conference on 25-28 Nov. 2007 Page(s):516-521.
  • Ravi Sankar Chandu. Ramana Murthy, G.  “Accreditation through outcome-based criteria - The ABET way”, 36th ISTE Annual Convention & Natural Seminar Conference on Competitiveness & Quality in Technical Education, Mapping Global Standards in Technical Education-II, December 2006, India.